Overview
The 8051 family of micro controllers is based on an architecture which is highly optimized for embedded
control systems. It is used in a wide variety of applications from military equipment to automobiles to the
keyboard on your PC. Second only to the Motorola 68HC11 in eight bit processors sales, the 8051
family of microcontrollers is available in a wide array of variations from manufacturers such as Intel,
Philips, and Siemens. These manufacturers have added numerous features and peripherals to the 8051
such as I2C interfaces, analog to digital converters, watchdog timers, and pulse width modulated outputs.
Variations of the 8051 with clock speeds up to 40MHz and voltage requirements down to 1.5 volts are
available. This wide range of parts based on one core makes the 8051 family an excellent choice as the
base architecture for a company's entire line of products since it can perform many functions and
developers will only have to learn this one platform.
The basic architecture consists of the following features:
- an eight bit ALU
- 32 descrete I/O pins (4 groups of 8) which can be individually accessed
- two 16 bit timer/counters
- full duplex UART
- 6 interrupt sources with 2 priority levels
- 128 bytes of on board RAM
- separate 64K byte address spaces for DATA and CODE memory
One 8051 processor cycle consists of twelve oscillator periods. Each of the twelve oscillator periods is
used for a special function by the 8051 core such as op code fetches and samples of the interrupt daisy
chain for pending interrupts. The time required for any 8051 instruction can be computed by dividing the
clock frequency by 12, inverting that result and multiplying it by the number of processor cycles required
by the instruction in question. Therefore, if you have a system which is using an 11.059MHz clock, you
can compute the number of instructions per second by dividing this value by 12. This gives an
instruction frequency of 921583 instructions per second. Inverting this will provide the amount of time
taken by each instruction cycle (1.085 microseconds).
Memory Organization
The 8051 architecture provides the user with three physically distinct memory spaces which can be seen
in the below figure. Each memory space consists of contiguous addresses from 0 to the maximum size, in
bytes, of the memory space. Address overlaps are resolved by utilizing instructions which refer
specifically to a given address space. The three memory spaces function as described below.
in the below figure. Each memory space consists of contiguous addresses from 0 to the maximum size, in
bytes, of the memory space. Address overlaps are resolved by utilizing instructions which refer
specifically to a given address space. The three memory spaces function as described below.
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| 8051 Memory Architecture |
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Related & useful Posts:
http://embeddsystems.blogspot.com/2011/11/89s-series-programmer-using-parallel.html
